Texas Instruments OMAP5912 Reference Manual page 1421

USB Device Controller
3.7.3 Non-Autodecoded Control Write Transfers
Non-autodecoded control write transfers include the
SET_/CLEAR_ENDPOINT feature, SET_CONFIGURATION,
SET_INTERFACE, SET_DESCRIPTOR and class- or vendor-specific control
write transfers. Non-autodecoded control write transfers consist of two or three
stages [setup, data (optional), and status].
The setup stage of a valid non-autodecoded control write transfer consists of
one SETUP transaction from USB host to USB device. At the end of the setup
stage handshake, the USB module generates an MPU general USB interrupt
with the IRQ_SRC.SETUP flag set. The MPU must respond to this general
USB interrupt by setting EP_NUM.SETUP_SEL bit, which clears the setup
interrupt flag. The MPU must then read 8 bytes from the setup FIFO via the
DATA register, clear EP_NUM.EP_SEL bit, and check the IRQ_SRC.SETUP
flag. If the IRQ_SRC.SETUP flag is set, the MPU must discard the setup data
it has just read and handle the new setup data packet following the same
scheme. If the IRQ_SRC.SETUP flag is cleared, the MPU code interprets this
request information and performs any application-specific activity needed
because of the setup stage request. If there is one or more data stage for the
transfer, the MPU must set the CTRL.SET_FIFO_EN bit for endpoint 0 to allow
the core to accept RX data from the coming OUT transaction.
The data stage for non-autodecoded control writes consists of zero or more
OUT transactions. Transaction handshaking and interrupt generation as for
non-isochronous, non-control OUT endpoints applies. The MPU can cause
NAK, STALL, or ACK signaling for the data stage transactions. If ACK was
signaled on a given general USB interrupt, the MPU must respond by reading
the data from the endpoint 0 RX FIFO and saving it for processing.
After completion of the data stage, a status stage IN transaction occurs. The
USB module provides handshaking to the USB host based on the endpoint 0
handshaking control bit STAT_FLG.FIFO_EN. The MPU can delay signaling
completion of the control write transfer by forcing NAK handshaking to the host
during the status stage (by holding STAT_FLG.FIFO_EN 0), or causing ACK
handshaking by setting the CTRL.SET_FIFO_EN bit with an empty endpoint
0 FIFO. An endpoint 0 TX general USB interrupt is sent to the MPU at
completion of the status stage.
After a SET_CONFIGURATION request, the device moves in addressed or
configured state as soon as the MPU sets the SYSCON2.DEV_CFG or
SYSCON2.CLR_CFG bits.
SPRU761A Universal Serial Bus (USB) 129