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Figure 73.
Transmit FIFO DMA Request Generation (56 Spaces)
TX buffer max
Programmable
threshold
Zero byte
DMA Active periods,this
does not represent the
DMA signalling
SPRU760B
The DMA request is again asserted if the FIFO is able to receive the number
of bytes defined by the TLR register. (See Table 88.)
The threshold can be programmed in a number of ways. See Figure 73 for an
example of a DMA transfer that operates with a space setting of 56, which
could arise from the use of the autosettings in the FCR[5:4] or the use of the
TLR[3:0] concatenated with the FCR[5:4]. The setting of 56 spaces in the
UART_IrDA should correlate with settings of the system DMA so that the buffer
does not overflow (program the DMA request size of the local host controller
to be equal to the number of spaces value in the UART).
Figure 74 shows another example with 8 spaces, to illustrate the buffer level
crossing the space threshold. Again, the local host DMA controller settings
must correspond to those of the UART_IrDA.
UARTs
56 spaces
Time
Example, DMA disabled to
illustrate the end of the
transfer
Serial Interfaces
187
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