Texas Instruments OMAP5912 Reference Manual page 1359

2.17 USB Host Controller OHCI Reset
2.18 USB Host Controller Power Management
SPRU761A
peripherals, including the USB host controller. When held in reset, the USB
host controller does not generate any USB activity on its USB ports. The USB
host controller requires that its 48-MHz clock input (from the OMAP5912
ULPD module) be active and that UHOST_EN be set (see Table 64, OTG
System Configuration Register 2 (OTG_SYSCON_2)) in order to complete its
reset sequence.
There is a delay of approximately 72 cycles of the ULPD USB host controller
48-MHz clock before the USB host controller is successfully reset. This delay
starts at the latest of the PER_EN bit set, UHOST_EN set, or 48-MHz clock
start. When the USB host controller is in hardware reset, read or write
accesses to its registers have no effect. It is recommended that USB host
controller software read the HCREVISION and HCHCCA registers after
deasserting reset to verify the proper reset values. If the read values for both
HCREVISION and HCHCCA are not correct, reset the values and continue
reading until the proper reset values are seen.
The UHOST_EN bit, when cleared, also holds the USB host controller in a
hardware reset. While the USB host controller is in reset, reads from the USB
host controller registers do not return valid data, and writes to the USB host
controller registers have no effect. When UHOST_EN is cleared, all USB host
controller internal state information is lost.
Software that initializes the USB host controller must ensure that the reset is
turned off, that the ULPD 48-MHz clock for the USB host controller is enabled,
and that UHOST_EN is set. It must then wait until reads of both the
HCREVISION register and the HCHCCA register return their correct reset
default values.
The OHCI Specification for USB provides the HCR bit in the
HCCOMMANDSTATUS register, which resets the OHCI controller. This reset
can be used to reset the OHCI functionality and has no effect on the USB host
controller OCPI and the MPU public peripheral bus interfaces. The OHCI reset
does not affect the USB host controller clock.
Power management of the OMAP5912 USB host controller is limited to
disabling the clock to the USB host by clearing UHOST_EN (see (see
Table 64, OTG System Configuration Register 2 (OTG_SYSCON_2)). When
UHOST_EN is 0, the USB host controller clocks are disabled and the USB host
controller is held in reset. The USB signal multiplexing controlled by
USB Host Controller
Universal Serial Bus (USB) 67