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Table 35. Control Register (CTRL)
Bit
Name
15:8
−
†
7
CLR_HALT
†
6
SET_HALT
5:3
−
† It is not required to set EP_NUM.EP_SEL bit before setting this bit. If this bit is set during the handling of an interrupt to the
endpoint, however, the USB device controller must not set EP_NUM.EP_SEL bit before setting CTRL.CLR_HALT bit, in order
to avoid a possible effect on interrupts . The USB device controller must check that FIFO is empty before setting the halt fea-
ture for the endpoint. A STALL transaction clears the FIFO.
SPRU761A
Description
Reserved
The clear halt endpoint (non-ISO) bit only concerns non-ISO endpoints—used
by the USB device controller to clear an endpoint halt condition:
0: No action
1: Clear halt condition
Always read 0
The set halt endpoint (non-ISO) only concerns non-ISO endpoints—used by
the USB device controller to halt the selected endpoint.
The halted endpoint returns STALL handshakes to the USB host. The USB
device controller can disable the endpoint interrupt if it does not want to be
informed of STALL handshakes.
Note: If the endpoint to halt is used by a DMA channel, the USB device
controller must disable the DMA channel before setting halt condition for this
endpoint.
0: No action
1: Halt endpoint
Always read 0
Reserved
USB Device Controller
Universal Serial Bus (USB)
73
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