Texas Instruments OMAP5912 Reference Manual page 1413

3.5.3 Isochronous OUT Endpoint FIFO Error Conditions
3.6 Isochronous IN (MPU->USB HOST) Transactions
SPRU761A
FIFO that was background in that frame is foreground, the FIFO is empty (a
0-length data ISO OUT transaction also results in an empty FIFO and cannot
be distinguished from a missed ISO OUT transaction).
If an ISO OUT transaction occurs with data error (CRC, PID check, or bit
stuffing), the RX FIFO is empty at the next SOF interrupt, and the
STAT_FLG.ISO_ERR bit is asserted for the duration of the next frame.
The MPU must never read more data than the value given by
RXFSTAT.RXF_COUNT.
If the USB host sends more data than the FIFO can contain, the FIFO is
cleared and the STAT_FLG.ISO_ERR is set at the next SOF interrupt. A
properly configured USB system does not do this.
Note:
Both foreground and background isochronous FIFOs are cleared when the
CTRL.CLR_EP bit is set.
Isochronous IN transactions are USB transactions in which a given amount of
data is transferred from the USB device controller module device to the USB
host every 1-ms USB frame. No handshaking is provided.
The USB module provides double-buffering of data for ISO IN endpoints; the
background FIFO is used as the source of data for IN transactions to the ISO
endpoint, and the foreground FIFO can be written to by the MPU. When an IN
transaction to an ISO endpoint occurs, the USB module sends all data found
in the endpoint background TX FIFO. The MPU is responsible for providing
new data to the isochronous IN endpoint foreground TX FIFO at each start of
frame interrupt.
In response to the SOF interrupt, for each isochronous IN endpoint, MPU code
selects the endpoint (via the EP_NUM register), and then fills the endpoint TX
FIFO (via the DATA register). Once all the transmit data have been written to
the FIFO, the MPU code must clear the EP_NUM.EP_SEL bit.
Because the USB transaction for the isochronous endpoint can occur at any
time during the USB 1-ms frame, the USB interface implements a
double-buffering of the endpoint transmit data FIFO. The endpoint includes
two FIFOs, each of which is the length of the configured isochronous endpoint.
USB Device Controller
Universal Serial Bus (USB) 121