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Packet Errors
3.4.3
Non-Isochronous IN Endpoint FIFO Error Conditions
3.5
Isochronous OUT (USB HOST-> MPU) Transactions
SPRU761A
If an error (CRC, bit stuffing, or PID check) occurs during the token packet of
a USB IN transaction to a non-isochronous endpoint, the USB block ignores
the transaction. No endpoint-specific interrupt to the MPU occurs for
transactions with corrupted packets. If the MPU clears the TX FIFO during the
data packet of an IN transaction, a bit stuffing error is forced.
If the USB host returns no handshake after an IN transaction (in case of an
error during transmission), the USB device controller module detects after a
time-out that an error has occurred. The data to transmit is still in the TX FIFO
to be re-sent during next IN transaction, STAT_FLG.FIFO_EN is not cleared,
and no interrupt is asserted to the MPU.
The MPU cannot write more data into the TX FIFO than the configured FIFO
size.
Isochronous OUT transactions are USB transactions in which a given amount
of data is transferred from the USB host to the USB device controller module
device every 1-ms USB frame. No USB handshaking is provided, and no
endpoint-specific interrupt to the MPU is generated at completion of an
isochronous OUT transaction. The MPU is responsible for handling
isochronous OUT data at each start of frame (SOF) interrupt.
At every SOF interrupt, for each isochronous OUT endpoint, MPU code must
select the endpoint by writing the appropriate value in the EP_NUM register
and check STAT_FLG.ISO_FIFO_EMPTY. If the RX FIFO contains data, code
must read the RXFSTAT.RXF_COUNT value (if the number of bytes to read
from RX FIFO is not known), read all the bytes from RX FIFO via the data
register, and then clear the EP_NUM.EP_SEL bit.
Because the USB transaction for the isochronous endpoint can occur at any
time during the USB 1-ms frame, the USB interface implements a
double-buffering of the endpoint receive data FIFO. The endpoint includes two
FIFOs, each of which is the length of the configured isochronous endpoint. At
all times, one of the two FIFOs is foreground and the other is background. The
USB interface side of the USB module is allowed to write to the background
RX FIFO, and the MPU is allowed to read to the foreground RX FIFO. The
designations foreground and background are swapped at each start of frame
(SOF). Isochronous endpoint FIFOs in the background are always enabled to
the USB, whereas the foreground FIFOs are enabled to the MPU.
USB Device Controller
Universal Serial Bus (USB)
119
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