Texas Instruments OMAP5912 Reference Manual page 1199

Multichannel Serial Interfaces
Table 52. Activity Control Register (CONTROL_REG) (Continued)
Bit Name
0 MCSI clock enable
Table 53. Interface Status Register (STATUS_REG)
Bit Name
15:7 Reserved
6 Reserved
5 TX underflow
4 TX ready
134 Serial Interfaces
Value Description
Enable clock of MCSI
module
0 Disable
1 Enable
Note:
The software reset is applied as long as the MCSI software reset bit is set
to 1. A software reset disables the MSCI (the MCSI clk enable bit is cleared)
and initializes the status register. It does not modify the other registers.
To clear an interrupt on the MCSI, the DSP must write to the MCSI status
register with the bit corresponding to the interrupt set to 1. The MCSI status
register has a two-cycle latency when writing into it, so the interrupt line is
cleared two cycles after a write. To prevent clearing the interrupt handler
before the interrupt line is cleared, the interrupt routine must be at least two
cycles long.
Value Description
Reserved bits. These bits
must always be written as 0.
Reserved bits. These bits
must always be written as 0.
Transmit underflow
0 No under
1 Under
Flag for transmit interrupt
occurrence
0 No interrupt
1 Interrupt
Hardware
Reset
Access
R/W 0
Hardware
Reset
Access
R 0000 0000 0
R/W 0
R 0
R/W 0
Software
Reset
0
Software
Reset
0000 0000 0
0
0
0
SPRU760B