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Figure 83.
HDQ and 1-Wire Overview
7.6
Software Interface
SPRU760B
MPU TIPB
(public)
Interrupt
Mapping the registers to the TI peripheral bus (TIPB) address signals is shown
in Table 113. The memory map identifies the 2K space associated with the
peripheral.
The hardware provides no synchronization between the register clock domain
and the state machine domain. This means that during a read, the hardware
has the capability to modify the receive buffer. It is also possible that any
access to the transmit write data register corrupts the data that is being sent
if a TX is being performed.
However, these hazards can be avoided in software by observing the following
limitations:
A read is not performed from the interrupt status register or receive buffer
-
register unless the processor has been interrupted by the peripheral.
After the release of the go bit in the control and status register, no access
-
to the TX write data buffer or the control and status registers is performed
until the processor has been interrupted by the peripheral.
Software is not allowed to poll the interrupt status register to determine
-
whether an interrupt was generated.
No register access can be done to the module registers after the software
-
puts the module in power-down mode (by setting bit 5 of the control and
status register to 0), except to reenable the clock.
0
HDQ / 1-Wire
Pin multiplexing for
GPIO11 device pin
HDQ and 1-Wire Protocols
TI
BQxxxx
device
Serial Interfaces
213
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