Texas Instruments OMAP5912 Reference Manual page 1273

HDQ and 1-Wire Protocols
7.3 1-Wire Bit Mode Operation
7.3.1 Timing Diagrams
208 Serial Interfaces
A single-bit mode can be entered by writing to the appropriate bit in the control
and status register. In this mode, only one bit of data is received each time from
the slave. After the bit is received, an RX complete interrupt is generated. Bit
0 of the receive buffer is updated each time a bit is received.
The mode has no effect in HDQ mode, as HDQ does not support single-bit
protocol.
Figure 78 shows the timing diagram for the read, reset, and write. In the HDQ,
the reset pulse contains only the initialization and not the presence pulse. The
timing required for the various signals are specified in Single-Wire Advanced
Battery Monitor IC for Cellular and PDA Applications (SLUS480).
The master works at the timing of the HDQ interface, which encompasses the
HDQ and the 1-Wire timing. Therefore, in 1-Wire mode, the master runs slower
than the full performance capability of the protocol.
SPRU760B