Texas Instruments OMAP5912 Reference Manual page 1287

Frame Adjustment Counter
Table 121. FAC Control and Configuration Register (CTRL)
Bit Name
15:3 Reserved
2 INT_ENABLE The INT_ENABLE bit is independent of the CNT bit. The
1 RUN
0 CNT
Table 122. FAC Status Register (STATUS)
Bit Name
15:1 Reserved
0 FSC_FULL
222 Serial Interfaces
Base Address = 0xFFFB A800, Offset Address = 0x08
Function
Reserved
interrupt can be enabled or disabled in either continuous
mode or halt mode.
0: No interrupt is generated
1: An interrupt is generated when FSC is updated.
Enables operation of the counter.
0: The frame start counter, the frame-synchronization
counter, and the FSC are reset to 0. Any pending interrupt
also is cleared when RUN is set to 0.
1: Enables the frame start counter.
0: Halt mode− updates FSC value when the
frame-adjustment reference count is met and halts operation
.
until FSC is read
1: Continuous mode− periodically updates FSC value each
time the frame-adjustment reference count is met.
Base Address = 0xFFFB A800, Offset Address = 0x0C
Function
Reserved
This bit is set to a 1 when FSC is updated. This bit is set
back to a 0 when the FSC has been read or RUN bit in
control is 0.
The status register (STATUS) contains an interrupt status bit.
.
R/W Reset
R 0x0000
R/W 0
R/W 0
R/W 0
R/W Reset
R 0x0000
R/C 0
SPRU760B