Texas Instruments OMAP5912 Reference Manual page 1406

USB Device Controller
Packet Errors
Sequence Bit Errors
3.3.3 Non-Isochronous, Non-Control OUT Endpoint FIFO Error Conditions
114 Universal Serial Bus (USB)
status from STAT_FLG. STAT_FLG.STALL is set to indicate that the endpoint
received a transaction to which the USB module signaled STALL
handshaking.
If STAT_FLG.EP_HALTED has been set by the MPU and can be removed, the
MPU must set CTRL.CLR_HALT to clear the condition and set
CTRL.SET_FIFO_EN to allow the next USB OUT transaction to the endpoint
to be placed into the RX FIFO. If STAT_FLG.EP_HALTED has been set in
response to a SET_FEATURE request sent by the USB host, or if the bit is
cleared (control transaction only), the MPU has no action to perform and must
clear the EP_NUM.EP_SEL bit. This clears the STAT_FLG.STALL bit for this
endpoint and allows the next transaction status to be written into the
STAT_FLG register.
In case of a receive data error during an endpoint OUT transaction (token or
data packet), the USB module does not provide a handshake during the
handshake phase of the transaction and no interrupt is asserted to the MPU
(the fourth case shown in Figure 4). Additionally, the endpoint RX FIFO is not
filled, and STAT_FLG.FIFO_EN bit is not cleared. If the MPU clears the RX
FIFO during the data packet of an OUT transaction, no handshake is returned
to the USB host to signal an error.
If the core does not receive expected DATA PID during an OUT transaction,
the module automatically returns ACK handshake to the USB host, regardless
of the STAT_FLG.FIFO_EN bit (per the USB specification). Data is ignored,
and no interrupt is asserted to the MPU.
This error occurs if ACK handshake from previous OUT transaction is received
corrupted by the USB host.
If the USB host attempts to fill more data into an endpoint RX FIFO than the
FIFO can hold, a FIFO overrun occurs. The USB module does not provide a
handshake during the handshake phase of the transaction and no interrupt is
asserted to the MPU. Additionally, the endpoint RX FIFO is not filled, and
STAT_FLG.FIFO_EN bit is not cleared.
The MPU must not read more data from RX FIFO than the value indicated by
RXFSTAT.RXF_COUNT.
SPRU761A