Texas Instruments OMAP5912 Reference Manual page 1237

UARTs
Table 106. System Configuration Register (SYSC)
Bit Name
7:5 −
4:3 IdleMode
2 EnaWakeUp
1 SoftReset
0 AutoIdle
Table 107. System Status Register (SYSS)
Bit Name
7:1 −
0 ResetDone
172 Serial Interfaces
Function
Reserved
Power management request/acknowledge control
00: Force idle. An idle request is acknowledged
unconditionally.
01: No idle. An idle request is never
acknowledged.
10: Smart idle. Acknowledgement to an idle
request is given based on the internal activity of
the module.
11: Reserved.
Ref: OCP design guidelines version 1.1
Wake-up feature control
0: Wake up is disabled.
1: Wake-up capability is enabled.
Software reset
Set this bit to 1 to trigger a module reset. This bit is
automatically reset by the hardware. During reads
it always returns a 0.
0: Normal mode.
1: The module is reset.
Internal OCP clock gating strategy
0: Clock is running.
1: Automatic OCP clock gating strategy is applied,
based on the OCP interface activity.
Offset Address (hex): 0x16 x S
Function
Reserved
Internal reset monitoring
0: Internal module reset is ongoing.
1: Reset completed.
Offset Address (hex): 0x17 x S
R/W Reset
R 000
R/W 00
R/W 0
R/W 0
R/W 0
R/W Reset
R 0000000
R 0
SPRU760B