Texas Instruments OMAP5912 Reference Manual page 1356

USB Host Controller
2.10 Cache Coherency in OHCI Data Structures and Data Buffers
2.11 OCPI Bus Addressing and OHCI Data Structure Pointers
64 Universal Serial Bus (USB)
The OMAP5912 traffic controller does not provide mechanisms to flush (or
writeback) the MPU cache when a DMA controller or OCPI access to system
memory occurs. Because there is no forced coherency mechanism, the
system implementation must ensure that the OMAP5912 USB host controller
can access the correct data from system memory and that the MPU accesses
that same data. This requires that any system memory accessed by the USB
host controller be allocated in non-cached system memory.
If the OHCI data structures and/or data buffers are allocated in cached portions
of system memory, a cache coherency problem can exist because the MPU
can read from, and, if in writeback mode, write to the cache; but the USB host
controller accesses are always directly to the physical system memory. If the
data structures are in a cached portion of system memory and writeback mode
is enabled, it is possible that the USB host controller can read stale data that
has not been updated by a cache writeback.
Similarly, if the data structure is in memory that is currently in the MPU cache
(either writeback or writethrough mode) and the OHCI controller modifies the
information in physical memory, the MPU can read stale data from the cache.
Cache coherency problems can be avoided by allocating the OHCI data
structures (HCCA, EDs, and TDs) and the USB data buffers in non-cacheable
system memory. In this case, every MPU access directly accesses physical
memory, so there is no coherency issue. Configuration of cacheable portions
of the MPU virtual address space is provided via the MPU memory
management unit. See the description of the MPU MMU in the OMAP3.2
Hardware
Engine Reference Guide (SWPU019C).
The USB host controller OHCI registers that point to the HCCA and the ED lists
must be programmed with values that correspond to the physical addresses
of the particular data structure. System software must use physical addresses
and not processor addresses when manipulating the OHCI control registers
that point to the HCCA, and to the ED and TD lists. System software must also
use physical addresses for the ED and TD pointers that are stored within ED
and TD entries.
The USB host controller driver software must also be able to examine the list
of completed transfer descriptors that the host controller creates as it retires
transfer descriptors. This list is pointed to by the HCDONEHEAD register,
which contains a physical address that points to the most recent transfer
SPRU761A