Texas Instruments OMAP5912 Reference Manual page 1322

USB Host Controller
Table 4. HC Command and Status Register (HCCOMMANDSTATUS)
Bit Name
31:18 Reserved
17:16 SOC
15 :4 Reserved
3 OCR
2 BLF
1 CLF
0 HCR
30 Universal Serial Bus (USB)
Description
Reserved
Scheduling overrun count
Counts the number of times a scheduling overrun occurs.
This count is incremented even if the host controller driver
has not acknowledged any previous pending scheduling
overrun interrupt.
Reserved
Ownership change request
This bit is set by the host controller driver to gain ownership
of the host controller.
OMAP5912 does not support SMI interrupts, so no
ownership change interrupt occurs.
Bulk list filled
The host controller driver must set this bit if it modifies the
bulk list to include new TDs. If HCBULKCURRENTED is 0,
the USB host controller does not begin processing bulk list
EDs unless this bit is set. When the USB host controller sees
this bit set and begins processing the bulk list, it clears this
bit.
Control list filled
The host controller driver must set this bit if it modifies the
control list to include new TDs. If HCCONTROLHEADED is
0, the USB host controller does not begin processing control
list EDs unless this bit is set. When the USB host controller
sees this bit set and begins processing the control list, it
clears this bit.
Host controller reset
Write of 0 has no effect.
1: This bit initiates a software reset of the USB host
controller. This transitions the USB host controller to the USB
suspend state. This resets most USB host controller OHCI
registers. OHCI register accesses must not be attempted
until a read of this register returns a 0. A write of 1 to this bit
does not reset the root hub and does not signal USB reset to
downstream USB functions.
The HC interrupt status register reports the status of the USB host controller
internal interrupt sources.
Type Reset
R 00
R/W 0
R/W 0
R/W 0
R/W 0
SPRU761A