Irda Modes; Idle Modes; Break And Time-Out Conditions; Time-Out Counter - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

IrDA Modes

Serial Interfaces

Writing to the divisor latches, DLL and DLH, to set the baud clock, BCLK,

must not be done during sleep mode. Therefore, it is advisable to disable

sleep mode using IER[4] before writing to DLL or DLH.

In IrDA modes, sleep mode is enabled by writing a 1 to MDR1[3].

Sleep mode is entered when

The serial data input line, RXIR, is idle.

The TX FIFO and TX shift register are empty.

The RX FIFO is empty.

There are no interrupts pending except THR interrupts.

The module wakes up when any change is detected on the RXIR line, if data

is written to the TX FIFO.

Sleep and autoidle modes are embedded power-saving features. At the

system level, power reduction techniques are applied by shutting down certain

internal clock and power domains of the device.

The UART supports REQ_IDLE ACK handshaking protocol. This protocol is

used at system level to shut down UART clocks in a clean and controlled

manner, and to switch the UART from the interrupt generation mode to a

wake-up generation mode for unmasked events (Refer to SYSC[2] and WER.)

For a software programming guide, refer to the OCP Design Guidelines for Idle

Mode Control.

An RX idle condition is detected when the receiver line, RX, has been high for

a time equivalent to 4X programmed word length+12 bits. The receiver line is

sampled midway through each bit.

For sleep mode, the counter is reset when there is activity on the RX line.

Table of Contents