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USB Device Controller
Table 51.
Receive DMA Control Register n (RXDMAn)
Bit
Name
15
RXn_STOP
14:8
Reserved
7:0
RXn_TC
102
Universal Serial Bus (USB)
Description
Receive DMA channel n transfer stop. When this bit is set, an RXn_EOT
interrupt is asserted to the USB device controller after n OUT transactions where
n is the encoded binary value + 1 programmed into RXDMAn.RXn_TC field. This
register is used when no smaller than buffer size packet is received at an
end-of-transfer (EOT), and the USB device controller expects a given amount of
data for the transfer.
Caution. At end of transfer, the DMA channel is disabled and all OUT
transactions received to the assigned endpoint are sent NAK by the core. The
USB device controller must set CTRL.SET_FIFO_EN for the endpoint to
reenable the channel.
Values after MPU or USB reset are low.
Reserved
Receive DMA channel n transactions count. The USB device controller can ask
for an interrupt each n OUT transactions where n is the encoded binary value +
1 programmed into RXDMAn.RXn_TC field. This register must be programmed
to the desired transaction watermark limit prior to enabling the DMA transfer for
the receive DMA channel n.
Caution: A reached watermark does not disable an active DMA transfer if
RXDMAn.RXn_STOP was not set. If RXDMAn.RXn_STOP was set for the
transfer both RXn_CNT and RXn_EOT interrupts are asserted.
A read to that register returns the number of transactions remaining before the
IRQ_SRC.RXn_CNT interrupt flag is asserted. This read mode is only provided
for software debug purposes.
Values after MPU or USB reset are low (all 8 bits).
This read/write register monitors incoming OUT transactions during DMA
transfer on channel n (n=0,1,2).
SPRU761A
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