Table of Contents
Advertisement
Figure 86.
Synchronization Circuit for Frame Synchronization and Frame Start Signals
Frame sync/
TFF
frame start
System clock
Figure 87.
Synchronization Circuit Waveforms
Frame start/sync
TFF output
System clock
DFF1 output
DFF2 output
DFF3 output
XOR output
8.3
FAC Interrupt
8.4
FAC Clocks and Reset
SPRU760B
DFF1
Figure 87 shows the actual waveforms at the output of each flip-flop and the
XOR output.
The FAC generates one interrupt, FAC_IRQ (in halt mode when the FARC
value is met), connected to the MPU level 2 interrupt handler, line 0
(level-sensitive).
The FAC works with a clock (PCLK) provided by the ULPD from a request
generated by the USB function (DS_WAKE_REQ_ON).
The DS_WAKE_REQ_ON request does not wake up the system itself.
The ULPD module uses this request to generate an interrupt (ULPD_nIrq) to
the MPU, which wakes up the system via its wake-up request (WKUP_REQ).
Frame Adjustment Counter
DFF2
DFF3
Serial Interfaces
XOR
Synced
signal
219
Advertisement
Chapters
Table of Contents
