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Non-Acknowledged Transactions (NAK)
3.3.2
Non-Isochronous, Non-Control OUT Transaction Error Conditions
STALLed Transactions
SPRU761A
transaction to the endpoint to be placed into the RX FIFO, and then clears the
EP_NUM.EP_SEL bit. This clears the STAT_FLG.ACK bit for this endpoint to
allow next transaction status to be written into the STAT_FLG register.
The device can be configured via the SYSCON1.NAK_EN either to inform the
MPU of a NAKed transaction or not. If SYSCON1.NAK_EN is cleared, no
interrupt is asserted to the MPU if an OUT transaction completes with a NAK
handshake and STAT_FLG.NAK bit is not set. If SYSCON1.NAK_EN is set,
the USB module issues an endpoint-specific interrupt to the MPU at
completion of an OUT transaction to an endpoint, and STAT_FLG.NAK bit is
set. In response to the endpoint interrupt, the MPU must read EPN_STAT
register to identify the endpoint causing the interrupt, and then write a 1 to the
interrupt bit to clear it. The MPU must then set EP_NUM.EP_NUM to the
endpoint number and EP_NUM.EP_SEL to 1, and then read the endpoint
status from STAT_FLG. STAT_FLG.NAK is set to indicate that the endpoint
received a transaction to which the USB module signaled NAK handshaking.
The MPU must set the CTRL.SET_FIFO_EN bit to allow the next USB OUT
transaction to the endpoint to be placed into the RX FIFO, and then clear the
EP_NUM.EP_SEL bit. This clears the STAT_FLG.NAK bit for this endpoint to
allow the next transaction status to be written into the STAT_FLG register.
The USB module responds to an endpoint OUT transaction with a STALL
handshake to indicate an error condition on the endpoint either if the endpoint
STAT_FLG.EP_HALTED bit is set or if a request error occurs (control
transactions only). When an endpoint OUT transaction is given a STALL
handshake, the endpoint STAT_FLG.STALL bit is set and an endpoint-specific
interrupt is generated for the endpoint. STAT_FLG.FIFO_EN is of lower priority
than STAT_FLG.EP_HALTED; when the STAT_FLG.EP_HALTED bit is set
and transactions to the RX endpoint are stalled, regardless of the
STAT_FLG.FIFO_EN
STAT_FLG.FIFO_EN bit is automatically cleared at the end of the STALLed
transaction and RX FIFO is cleared.
In response to the endpoint interrupt, the MPU must read the EPN_STAT
register to identify the endpoint causing the interrupt, and then write a 1 to the
interrupt bit to clear it. The MPU must then set EP_NUM.EP_NUM to the
endpoint number and EP_NUM.EP_SEL to 1, and then read the endpoint
value.
If
STAT_FLG.FIFO_EN
Universal Serial Bus (USB)
USB Device Controller
is
set,
the
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