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USB Device Controller
2.19
OCPI Clocking
3
USB Device Controller
3.1
USB Device Controller Registers
Table 31. USB Device Controller Registers
Register
REV
EP_NUM
68
Universal Serial Bus (USB)
HMC_MODE is not affected, so a HMC_MODE setting that multiplexes USB
function controller and/or UART1 signals to OMAP5912 top-level multiplexing
can still make use of the USB function controller and/or UART1.
When the OMAP5912 host controller 48-MHz clock is disabled or UHOST_EN
is 0, all USB host controller OHCI registers and the HOSTUEADDR,
HOSTUESTATUS, HOSTTIMEOUTCTRL, and HOSTREVISION registers
are inaccessible.
The OCPI clock must be active to allow USB host controller access to system
memory. The OCPI clock is controlled by the ARM_IDLECT3.EN_OCPI_CK
and IDLOCPI_ARM bits.
The USB device controller supports the implementation of a full-speed device
fully compliant with the USB 1.1 standard.
It provides an interface between the MPU and the USB wire and handles USB
transactions with minimal MPU software intervention.
The USB device controller module supports one control endpoint (EP0), up to
15 IN endpoints, and up to 15 OUT endpoints. The exact endpoint
configuration is software programmable. The specific items of a configuration
are for each endpoint, the size in bytes, the direction (IN, OUT), the type
(bulk/interrupt or ISO), and the associated number.
The USB device controller module also supports three DMA channels for IN
endpoints and three DMA channels for OUT endpoints for either bulk/interrupt
or ISO transactions.
Table 31 lists the USB device controller registers. Table 32 through Table 54
describe the register bits.
Description
Revision
Endpoint
Endpoint selection
R/W
Address
0xFFFB4000
0xFFFB4004
SPRU761A
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