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USB Device Controller
Figure 7.
Isochronous IN Transaction Phases and Interrupts
Successful data transfer to PC host
ISO OUT Token
No handshake occurs. EP RX FIFO is empty after data sent. No EP interrupt
occurs. STAT_FLG is unchanged.
Reception of SOF causes SOF interrupt.
Note: An SOF interrupt is generated even if the SOF packet is corrupted.
SOF Token
SOF Interrupt
LH code for SOF ISR must fill all isochronous In EP TX FIFOs with new tranmit
data and pull new receive data from all isochronous Out EP RX FIFOs.
Indicates a packet received by the device
Indicates a packet sent by the device
3.6.1
Isochronous IN Endpoint Handshaking
122
Universal Serial Bus (USB)
At all times, one of the two FIFOs is foreground and the other is background.
The USB interface side of the USB module is allowed to read from the
background TX FIFO, and the MPU is allowed to write to the foreground TX
FIFO. The designations foreground and background are swapped, and the
new background TX FIFO is cleared at each start of frame (SOF). Because
ISO endpoints implement double-buffering, ISO endpoints do not control
access to the FIFOs via a CTRL.SET_FIFO_EN bit; the CTRL.SET_FIFO_EN
and the STAT_FLG.FIFO_EN bits are not implemented for ISO IN endpoints.
Figure 7 shows the transaction phases associated with isochronous IN
transactions and the SOF transaction. No endpoint-specific interrupt to the
MPU is generated as a result of an isochronous IN transaction, and there is
no handshake phase. The SOF transaction causes an SOF interrupt to the
MPU; it is assumed that the MPU refills the isochronous IN endpoint transmit
FIFO at each SOF interrupt.
Data
Because isochronous endpoint transactions have no handshake packets, the
STAT_FLG.STALL,
STAT_FLG.NAK,
and
STAT_FLG.ACK
bits
for
SPRU761A
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