Texas Instruments OMAP5912 Reference Manual page 1214

Table 66. FIFO Control Register (FCR)
Bit Name
7:6 RX_FIFO_TRIG
5:4 TX_FIFO_TRIG
3 DMA_MODE
2 TX_FIFO_CLEAR
1 RX_FIFO_CLEAR
0 FIFO_EN
Notes: 1) Bits 4 and 5 can only be written to when EFR[4] = 1.
2) Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0).
3) See for FCR[5:4] setting restriction when SCR[6] = 1.
4) See for FCR[7:6] setting restriction when SCR[7] = 1.
SPRU760B
Function
Sets the trigger level for the RX FIFO:
If SCR[7] = 0 and TLR[7:4] = 0000:
00: 8 characters
01: 16 characters
10: 56 characters
11: 60 characters
If SCR[7] = 0 and TLR[7:4] non-0, RX_FIFO_TRIG
is not considered.
If SCR[7] = 1, RX_FIFO_TRIG is 2 LSB of the
trigger level (1−63 on 6 bits) with the granularity 1.
Sets the trigger level for the TX FIFO:
If SCR[6] = 0 and TLR[3:0] = 0000:
00: 8 spaces
01: 16 spaces
10: 32 spaces
11: 56 spaces
If SCR[6] = 0 and TLR[3:0] non-0, TX_FIFO_TRIG
is not considered.
If SCR[6] = 1, TX_FIFO_TRIG is 2 LSB of the
trigger level (1−63 on 6 bits) with the granularity 1.
0: DMA_MODE 0 (No DMA)
1: DMA_MODE 1 (UART_nDMA_REQ[0] in TX,
UART_nDMA_REQ[1] in RX)
This register is considered if SCR[0] = 0.
0: No change.
1: Clears the transmit FIFO and resets its counter
logic to 0. Returns to 0 after clearing FIFO.
0: No change.
1: Clears the receive FIFO and resets its counter
logic to 0. Returns to 0 after clearing FIFO.
0: Disables the transmit and receive FIFOs.
1: Enables the transmit and receive FIFOs.
UARTs
R/W Reset
W 00
W 00
W 0
W 0
W 0
W 0
Serial Interfaces 149