Texas Instruments OMAP5912 Reference Manual page 1233

UARTs
Table 97. Received Frame Length High Register (RXFLH)
Bit Name
7:4 −
3:0 RXFLH
Table 98. Status FIFO Line Status Register (SFLSR)
Bit Name
7:5 −
4 OE_ERROR
3 FRAME_TOO_LONG_
ERROR
2 ABORT_DETECT
1 CRC_ERROR
0 −
Table 99. Resume Register (RESUME)
Bit Name
7:0 RESUME
168 Serial Interfaces
Function
Reserved
MSB register used to specify the frame length in
reception
Offset Address (hex): 0x0A x S and read
IrDA modes only.
Reading this register in effect reads frame-status information from the status
FIFO. This register does not physically exist. Reading this register increments
the status FIFO read pointer (SFREGL and SFREGH must be read first).
Function
Reserved
1: Overrun error in RX FIFO when frame at top of
FIFO was received.
1: Frame-length too long error in frame at top of
FIFO.
1: Abort pattern detected in frame at top of FIFO.
1: CRC error in frame at top of FIFO.
Reserved
Offset Address (hex): 0x0B x S and read
IrDA modes only.
This register clears internal flags that halt transmission/reception when an
underrun/overrun error occurs. Reading this register resumes the halted
operation. This register does not physically exist and reads always as 0x00.
Function
Dummy read to restart the TX or RX
R/W Reset
R 0x0
W 0x0
R/W Reset
R 000
R Unknown
R Unknown
R Unknown
R Unknown
R 0
R/W Reset
R 0x00
SPRU760B