Table of Contents
Advertisement
Table 120. Frame Start Count Register (FSC)
Bit
Name
15:0
FS
SPRU760B
A level-sensitive interrupt can be generated to indicate that the frame-start
counting is finished, and the FSC register is loaded with a new count value.
The interrupt is controlled by the INT_ENABLE bit in the control and
configuration (CTRL) register. If this bit is set to 1, an interrupt is generated
when the FSC register is updated. Because the interrupt is level-sensitive, the
interrupt signal is kept low until the software reads the FSC register, or the RUN
bit in the control register is set to 0. When the FSC is read or RUN bit in control
register is set to 0, the interrupt signal is reset to 1. When the IN_ENABLE bit
is set to 0, no interrupt is generated. The interrupt can be enabled or disabled
for both continuous mode and halt mode.
Base Address = 0xFFFB A800, Offset Address = 0x04
Function
16-bit value
The control and configuration (CTRL) register is a R/W register used to
configure the module. The RUN bit enables the frame-start counter. If this bit
is set to 0, the frame-start counting is disabled immediately. The software can
use this bit as a software reset for the FAC module by setting the RUN bit to 0.
When the RUN bit is set to 0, the frame-start counter, the frame-synchronization
counter, and the FSC register are reset to 0. The software reset also clears the
status register FSC_FULL bit to 0. If an interrupt has been generated and the
FAC module is waiting for an FSC register read, a software reset puts the
counter control back to idle state. This means that after the software has been
reset the counter starts counting again, regardless of whether the FSC register
has been read or not.
Frame Adjustment Counter
R/W
Reset
R
0x0000
Serial Interfaces
221
Advertisement
Chapters
Table of Contents
