Texas Instruments OMAP5912 Reference Manual page 1326

USB Host Controller
Table 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) (Continued)
Bit Name
1 WDH
0 SO
Table 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE)
Bit Name
31 MIE
30 OC
29 :7 Reserved
6 RHSC
34 Universal Serial Bus (USB)
Description
Write done head
When 1 and MIE is 1, allows write done head interrupts to
propagate to the OMAP5912 level 2 interrupt controller.
When 0, or when MIE is 0, write done head interrupts do
not propagate.
A write of 0 has no effect on this bit.
A write of 1 sets this bit.
Scheduling overrun
When 1 and MIE is 1, allows scheduling overrun interrupts
to propagate to the OMAP5912 level 2 interrupt controller.
When 0, or when MIE is 0, scheduling overrun interrupts do
not propagate.
A write of 0 has no effect on this bit.
A write of 1 sets this bit.
The HC interrupt disable register is used to clear bits in the
HCINTERRUPTENABLE register.
Description
Master interrupt enable
Read always returns 0.
Write of 0 has no effect.
Write of 1 clears the HCINTERRUPTENABLE MIE bit.
Ownership change
This bit has no effect on OMAP5912.
Reserved
Root hub status change
Read always returns 0.
Write of 0 has no effect.
Write of 1 clears the HCINTERRUPTENABLE RHSC bit.
Type Reset
R/W 0
R/W 0
Type Reset
R/W 0
R 0
R/W 0
SPRU761A