Texas Instruments OMAP5912 Reference Manual page 1216

Table 68. Line Control Register (LCR)
Bit Name
7 DIV_EN
6 BREAK_EN
5 PARITY_TYPE2
4 PARITY_TYPE1
3 PARITY_EN
2 NB_STOP
1:0 CHAR_LENGTH
SPRU760B
Function
0: Normal operating condition.
1: Divisor latch enable. Allows access to DLL,
DLH, and other registers (refer to the registers'
mapping).
Break control bit
0: Normal operating condition.
1: Forces the transmitter output to go low to alert
the communication terminal.
0: Odd parity is generated (if LCR[3] = 1).
1: Even parity is generated (if LCR[3] = 1).
0: No parity.
1: A parity bit is generated during transmission and
the receiver checks for received parity.
Specifies the number of stop bits:
0: 1 stop bits (word length = 5, 6, 7, 8)
1: 1.5 stop bits (word length = 5)
1−2 stop bits (word length = 6, 7, 8)
Specifies the word length to be transmitted or
received
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
Offset Address (hex): 0x05 x S and LCR is not 0xBF and read
UARTs
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 00
Serial Interfaces 151