Texas Instruments OMAP5912 Reference Manual page 1280

Multimedia processor device overview and architecture
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Table 116. HDQ/1−Wire Control Register (HDQ1W_CTRL)
Bit
Name
31:24
Reserved
23:16
Reserved
15:8
Reserved
7
SBM
6
IM
5
PDM
4
GB
3
PD
2
IP
1
RWB
0
MODE
Table 117. HDQ/1−Wire Interrupt Status Register (HDQ1W_INTS)
Bit
Name
31:24
Reserved
23:16
Reserved
15:8
Reserved
7:3
Reserved
2
TC
SPRU760B
Base Address = 0xFFFB C000, Offset Address = 0x08
Function
Reserved − read aliased to bit 7:0, writes ignored
Reserved − read aliased to bit 7:0, writes ignored
Reserved − read aliased to bit 7:0, writes ignored
Single-bit mode for 1-Wire
Interrupt mask (1: Enable, 0: Disable interrupts)
Power-down mode (1: Enable clocks, 0: Disable clocks)
Go bit
Write 1 to send the appropriate commands.
Bit returns to 0 after the command is complete.
Presence detect received, 1-Wire mode only.
.
0: Not detected
1: Detected.
Write 1 to send Initialization pulse. Bit returns to 0 after pulse
is sent.
R/W bit (determines if next command is read or write)
.
0: Write
1: Read.
Set mode
.
0: HDQ
1: 1-Wire.
Base Address = 0xFFFB C000, Offset Address = 0x0C
Function
Reserved − read aliased to bit 7:0, writes ignored
Reserved − read aliased to bit 7:0, writes ignored
Reserved − read aliased to bit 7:0, writes ignored
Reserved − reads 0, writes ignored
TX completed
HDQ and 1-Wire Protocols
R/W
Reset
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Reset
R
0x00
R
0x00
R
0x00
R
0x0
R/C
0
Serial Interfaces
215

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