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Table 36. Status Register (STAT_FLG)
Bit
Name
15
NO_RXPACKET
14
MISS_IN
13
DATA_FLUSH
SPRU761A
This set-only register controls the FIFO and status of the selected endpoint.
A read access to this register always returns 0.
Endpoint 0 setup FIFO is always enabled and ready to accept setup data. No
control register CTRL is implemented for this FIFO because the USB device
controller cannot control it.
Description
The isochronous no packet received (ISO OUT) bit only concerns
ISO OUT endpoints.This bit notifies the USB device controller that the
core has not received any isochronous packet on the endpoint. This
bit is updated on a SOF (start of frame).
0: The endpoint received a packet on the previous frame.
1: The endpoint did not receive a packet on the previous frame.
Value after MPU or USB reset is high.
The isochronous missed IN token for the previous frame (ISO IN) bit
only concerns ISO IN endpoints.This bit notifies the USB device
controller that the core missed a valid ISO IN token during the
previous frame and that TX data were flushed from the FIFO instead
of being transmitted to the USB host.
This bit is updated on a SOF (start of frame).
0: The endpoint received an IN token the previous frame.
1: The endpoint did not receive an IN token the previous frame and
TX data were flushed.
Value after MPU or USB reset is low.
The isochronous receive data flush (ISO OUT) bit only concerns ISO
OUT endpoints. When set, this bit indicates that data were flushed
from the isochronous FIFO that was moved from the foreground to
the background. This happens when the USB device controller does
not read all of the data from the foreground FIFO in a frame.
This bit is updated in every frame.
0: Not significant
1: Data was flushed.
Value after MPU or USB reset is low.
USB Device Controller
Universal Serial Bus (USB)
75
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