Texas Instruments OMAP5912 Reference Manual page 1366

USB Device Controller
Table 35. Control Register (CTRL) (Continued)
Bit Name
2 SET_FIFO_EN
1 CLR_EP
0 RESET_EP
† It is not required to set EP_NUM.EP_SEL bit before setting this bit. If this bit is set during the handling of an interrupt to the
endpoint, however, the USB device controller must not set EP_NUM.EP_SEL bit before setting CTRL.CLR_HALT bit, in order
to avoid a possible effect on interrupts . The USB device controller must check that FIFO is empty before setting the halt fea-
ture for the endpoint. A STALL transaction clears the FIFO.
74 Universal Serial Bus (USB)
Description
†
The set FIFO enable (non-ISO) bit only concerns non-ISO endpoints. If the
selected endpoint direction is IN, the USB device controller uses this bit to
enable the USB device to transmit data from the FIFO at the next valid IN
token. If the selected endpoint direction is OUT, the USB device controller uses
this bit to enable the USB device to receive data from the USB host at the next
valid OUT transaction. If not, setting the device returns a NAK handshake.
ISO endpoints FIFO are always enabled.
Note: The USB device controller must never enable endpoint 0 FIFO out of
control transfers. For bulk and interrupt endpoints, FIFO must never be
enabled when the halt feature is set or when RX FIFO is not empty.
Furthermore, during EP interrupts handling, the USB device controller must
have cleared the interrupt bit before setting CTRL.SET_FIFO_EN bit (to avoid
masked ACK interrupts).
0: No action
1: FIFO enabled
Always read 0
Clear endpoint: the USB device controller sets this bit to clear the selected
endpoint FIFO pointers and flags. This bit resets the FIFO pointers, the FIFO
empty status bit is set, and the FIFO enable bit and other FIFO flags are
cleared upon completion of the FIFO reset. It also clears the previous
transaction handshake status. For ISO endpoints or non-ISO double-buffered
endpoints, both foreground and background FIFO are cleared.
0: No action
1: Clear endpoint
Always read 0
The endpoint reset (non-control) bit only concerns non-control endpoints.The
USB device controller sets this bit to reset the selected endpoint. It forces an
interrupt or a bulk endpoint data PID to DATA0, clears the halt condition, and
clears the FIFO (both foreground and background if endpoint is
double-buffered) and previous transactions handshake status. For an ISO
endpoint, it only clears the FIFO (both foreground and background).
0: No action
1: Reset endpoint
Always read 0
SPRU761A