Texas Instruments OMAP5912 Reference Manual page 1391

Table 49. DMA FIFO Data Register (DATA_DMA)
Bit Name
15:0 DATA_DMA
SPRU761A
Description
DMA FIFO data. When an RX DMA request is active for a channel (only one
active at a given time), this register contains the data that the core received from
the USB host OUT transaction using this channel. Data can be accessed by the
main DMA controller engine (read access) in response to the DMA request for the
channel.
When a TX DMA request is active for a channel (only one active at a given time),
this register contains the data written by the main DMA controller engine (write
access) in response to a DMA request for the transmit channel to be sent to the
USB host during the next IN transaction.
Warning: It is possible for both an RX DMA request and a TX DMA request to be
active at the same time. In this case, the main DMA controller engine can access
both transmit endpoint and receive endpoint FIFO. A read access to DATA_DMA
register affects the endpoint that caused the RX DMA request to be active, and a
write access affects the endpoint that caused the TX DMA request to be active.
Caution: The USB device controller must not access this register directly;
however, there is no hardware mechanism to prevent such access. No access
into this register must be made out of DMA request handling.
This register is the entry point to write or to read data into/from an endpoint
used in a DMA transfer through DMA channel 0, 1 or 2.
USB Device Controller
Universal Serial Bus (USB) 99