Texas Instruments OMAP5912 Reference Manual page 1277

Multimedia processor device overview and architecture
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HDQ and 1-Wire Protocols
7.4
Power-Down Mode
7.5
HDQ and 1-Wire Battery Monitoring Serial Interface
212
Serial Interfaces
Presence detect/time-out
-
In 1-Wire mode, it indicates that it is now valid to check the presence
J
detect received bit. Cleared at beginning of initialization sequence.
In HDQ mode, it indicates that after a read command was issued by
J
the host, the slave did not pull the line low within the specified time. In
HDQ mode, the bit is cleared at beginning of the read command.
Only one interrupt is generated to the microcontroller, based on any of the
above interrupt status conditions. A read to the interrupt status register clears
all of the status bits that have been set.
The interrupt can be masked by setting the appropriate bit in the control and
status register.
A read of the interrupt status register clears the interrupt. If there is a pending
interrupt, the interrupt line stays low and no low-high-low transition is created.
The interrupt therefore must be handled as a level interrupt (where a low-going
edge is not needed) in an upstream interrupt handler (or processor).
Writing to the appropriate bit in the control and status register shuts the clock
to the state machine. The state machines are reset when the clock is disabled,
and if any transaction is being performed, it is aborted into the reset state. The
register values are not affected by disabling the clock. No register access must
be performed to the module registers after the software puts the module in
power-down mode by setting bit 5 of the control and status register to 0, other
than a write to the power-down bit to take it out of power-down mode.
The HDQ and 1-Wire battery monitoring serial interface module implements
the hardware protocol of the master function of the Benchmarq HDQ and the
Dallas Semiconductor 1-Wire™ protocol. The module works off a command
structure that is programmed into transmit command registers. The received
data is in the received data register. The firmware is responsible for correct
sequencing in the command registers. The module implements only the
hardware interface layer of the protocols.
The HDQ and the 1-Wire mode are selectable in software, which must be done
before any transmit and receive from the module is performed. The mode is
assumed static during operation of the device.
SPRU760B

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