Texas Instruments OMAP5912 Reference Manual page 1236

Table 104. Auxiliary Control Register (ACREG) (Continued)
Bit Name
3 SEND_SIP
2 SCTX_EN
1 ABORT_EN
0 EOT_EN
Table 105. Module Version Register (MVR)
Bit Name
7:4 MAJOR_REV
3:0 MINOR_REV
Note: UART/IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART/IRDA with SIR, MIR, and FIR support is
revision 2.x (this specification).
SPRU760B
Function
MIR/FIR modes only
Send serial infrared interaction pulse (SIP)
0: No action.
1: Send SIP pulse.
If this bit is set during a MIR/FIR transmission, the
SIP is sent at the end of it.
This bit is automatically cleared at the end of the
SIP transmission.
Store and controlled TX start
When MDR1[5] = 1 and the LH writes 1 to this bit,
the TX state machine starts frame transmission.
This bit is self-clearing.
Frame abort
The LH can intentionally abort transmission of a
frame by writing 1 to this bit. Neither the end flag
nor the CRC bits are appended to the frame.
EOT (end of transmission) bit
The LH writes 1 to this bit just before it writes the
last byte to the TX FIFO in set-EOT bit frame
closing method. This bit is automatically cleared
when the LH writes to the THR (TX FIFO).
Offset Address (hex): 0x14 x S and read
Function
Major revision number of the module
Minor revision number of the module
Offset Address (hex):0x15 x S
The autoidle bit controls a power-saving technique to reduce the logic power
consumption of the OCP interface. That is, when the feature is enabled, the
clock is gated off until an OCP command for this device has been detected.
When the software reset bit is set high, it causes a full device reset.
UARTs
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W Reset
1
R
R −
Serial Interfaces 171