Texas Instruments OMAP5912 Reference Manual page 1266

6.7 UART Configuration Example
6.7.1 UART Software Reset
SPRU760B
The LH uses the frame-length information to locate the frame-boundary in the
received frame data. The LH screens bad frames using the error-status
information and later requests the sender to resend only the bad frames.
This status FIFO is used effectively in DMA, as the LH need not be interrupted
each time a frame is received but only when the programmed status FIFO
trigger level is reached.
This section outlines the programming stages for operating one UART module
with FIFO, interrupt, and no DMA capabilities. This is a three-step procedure
that ensures a quick start of these modules (obviously, it does not cover every
UART module feature). The first stage covers the software reset of the module
(interrupts, status, and controls). The second stage deals with FIFO
configuration and enable. The last stage with deals with the baud rate data and
stop configuration. The procedure below is programming language agnostic.
Goal:
To clear IER and MCR registers, remove UART breaks (LCR[6] = 0) and put
module in reset (MDR1[2:0] = 0x07).
Procedure:
To write into both the IER and MCR register EFR[4] must first be set to 1.
To be able to access the EFR register, 0xBF must be first be written to LCR
register. Hence,
1) LCR = 0xBF; First write to the LCR register.
2) EFR[4] = 1; When LCR = 0xBF, enable the enhanced feature register.
3) LCR[7] = 0; Here, access to IER and MCR is allowed.
4) IER = 0x00; Disable interrupt.
5) MCR = 0x00; Force control signals inactive.
6) LCR[6] = 0; Here, remove UART breaks.
7) MDR1 = 0x07; Here, UART is in reset or disabled.
Alternatively, the SYSC[1] can be set to one to instigate a hardware reset from
the generic synchronous reset module. The reset progress can be monitored
via the SYSS[0]. Once complete, the above sequence should ensure that the
UART is in the equivalent disabled mode with reference to MDR1[2:0].
UARTs
Serial Interfaces 201