Texas Instruments OMAP5912 Reference Manual page 1285

Frame Adjustment Counter
8.5 Software Interface
Table 118. FAC Registers
Register Description
FARC Frame adjustment reference count
FSC Frame start count
CTRL Control and configuration
STATUS Status
SYNC CNT Frame synchronization counter
START CNT Frame start counter
Table 119. Frame Adjustment Reference Count Register (FARC)
Bit Name
15:0 FARC
220 Serial Interfaces
Once the system is awakened (12 MHz provided to the MPU), the MPU
programmable peripheral clock (PERCLK) is used as the source clock for the
FAC clock.
The MPU TIPB reset (MPU_PER_RST) resets the FAC.
Table 118 lists the FAC registers. Table 119 through Table 122 describe the
register bits.
The FAC module is a word16 module with 32-bit aligned addresses.
The frame-adjustment counter register (FARC) is programmed with the
number of frame synchronization counts over which the frame start pulses are
counted. This is a 16-bit programmable fixed reference in the range of
0-65536. A value of 0 disables the count operation.
Base Address = 0xFFFB A800, Offset Address = 0x00
Function
16-bit value in the range 0-65536: 0—disable counting
The frame-start count (FSC) register is a 16-bit read-only register that contains
the number of frame-start rising edges that occur during the programmable
FARC period. The frame-start counting can be in one of two modes. When the
CNT bit in the control and configuration (CTRL) register is set to 1, the counting
is in continuous mode and this register is updated periodically (every time the
frame adjustment reference count is met) with the new count value. If CNT is
0, the counting is in halt mode. The frame-start count register is updated when
the frame adjustment reference count is met, and the counting halts until the
software reads the FSC register.
Type Address
R/W FFFB:A800
R FFFB:A804
R/W FFFB:A808
R FFFB:A80C
R FFFB:A810
R FFFB:A814
R/W Reset
R/W 0x0000
SPRU760B