Texas Instruments OMAP5912 Reference Manual page 1324

USB Host Controller
Table 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) (Continued)
Bit Name
1 WDH
0 SO
Table 6. HC Interrupt Enable Register (HCINTERRUPTENABLE)
Bit Name
31 MIE
30 OC
29 :7 Reserved
6 RHSC
32 Universal Serial Bus (USB)
Description
Write done head
When 1, indicates that the USB host controller has
updatedthe HCDONEHEAD register.
Write of 0 has no effect.
Write of 1 clears this bit. The host controller driver must read
the value from HCDONEHEAD before writing 1 to this bit.
Scheduling overrun
When 1, indicates that a scheduling overrun has occurred.
Write of 0 has no effect.
Write of 1 clears this bit.
The HC interrupt enable register (Table 6) enables various OHCI interrupt
sources to generate interrupts to the OMAP5912 level 2 interrupt handler.
Description
Master interrupt enable
When 1, allows other enabled OHCI interrupt sources to
propagate to the OMAP5912 level 2 interrupt controller.
When 0, OHCI interrupt sources are ignored and no USB
host controller interrupts are propagated to the OMAP5912
level 2 interrupt controller.
A write of 0 has no effect on this bit.
A write of 1 sets this bit.
Ownership change
This bit has no effect on OMAP5912.
Reserved
Root hub status change
When 1 and MIE is 1, allows root hub status change
interrupts to propagate to the OMAP5912 level 2 interrupt
controller.
When 0, or when MIE is 0, root hub status change
interrupts do not propagate.
A write of 0 has no effect on this bit.
A write of 1 sets this bit.
Type Reset
R/W 0
R/W 0
Type Reset
R/W 0
R 0
R/W 0
SPRU761A