Texas Instruments OMAP5912 Reference Manual page 1269

HDQ and 1-Wire Protocols
204 Serial Interfaces
In a typical write to the slave, 2 bytes of data are sent to the slave. This is the
command/address byte followed by the data that must be written. In a typical
read, 1 command/address byte is sent to the slave, and the slave returns 1
byte of data.
The master implementation is a byte engine. The firmware is responsible for
sending the ID, command/address, and data. The master engine provides
only one data TX register.
HDQ is a return-to-1 protocol. This means that after a data byte (either
command/address + write data for writes, or just command/address for reads)
is sent to the slave, the host pulls the line high. This is accomplished in the
device by setting the line to high (with an external pullup). The slave pulls the
line low to initiate a transaction. This is the case when a read occurs, and the
slave must send the read data back to the host.
If the host initiates a read and data is not received in a specified interval (the
slave does not pull the line low within this time), a time-out status bit is set. This
indicates that a read was not successfully completed. On successful
completion, the time-out bit is cleared. The bit remains set or cleared until the
next transaction by the host.
An interrupt condition indicates either a TX complete, RX complete, or time-out
condition. The read of the interrupt status register clears all of the interrupt
conditions. Only one interrupt signal is sent to the microcontroller, and only an
overall mask bit exists for the enabling and disabling of the interrupt. The
interrupt conditions cannot be individually masked.
The programmer must perform the following sequence for the reads and writes
to the slave:
Write operation:
1) Write the command or data value to the TX write register.
2) Write 0 to the R/W bit of the control and status register to indicate a write.
3) Write 1 to the go bit of the control and status register to start the actual
transmit. This step and the above step can be done at the same time.
The hardware sends the byte from the TX data register.
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The time-out bit is always cleared in a write, because the hardware
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has no acknowledge mechanism from the slave.
The completion of the operation sets the TX complete flag in the
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interrupt status register. If interrupts are masked, no interrupt is
generated. The interrupt status register is always cleared at the
beginning of any read or write operation.
At the end of the write, the go bit is cleared.
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