Texas Instruments OMAP5912 Reference Manual page 1371

Table 37. Receive FIFO Status Register (RXFSTAT)
Bit Name
15:10 −
9:0 RXF_COUNT
Table 38. System Configuration Register 1 (SYSCON1)
Bit Name
15:9 -
8 CFG_LOCK
SPRU761A
Note:
The updates for non-ISO transactions are done at the end of each
non-transparent and valid transaction to a given endpoint, if no non-handled
interrupt is pending on the endpoint.
The definition of a non-transparent, non-ISO IN transaction is one that re-
sponds with an ACK handshake or a STALL handshake, or optionally a NAK
handshake if SYSCON1.NAK_EN is asserted to 1. An ERR handshake or
a NAK handshake when SYSCON1.NAK_EN is 0 is considered transparent.
A write to this register has no effect.
Description
Reserved
The receive FIFO byte count 10-bit field indicates the number of bytes currently in
the receive FIFO.
Values after MPU or USB reset is low (all 10 bits).
This read-only register indicates how many bytes are in the receive FIFO for
the selected endpoint. A write to this register has no effect. The USB device
controller cannot read this register if the EP_NUM.EP_SEL bit is not set for the
endpoint. No receive FIFO status exists for the setup FIFO, because 8 bytes
are always expected.
Description
Reserved
Device configuration locked bit: after the USB device controller has entered
the device configuration (registers 0x20 to 0x3F), it must set the
CFG_LOCK bit so that the device can be used. When the device
configuration is not locked, the device is not ready to be used:
0: Device configuration is not locked. Device is not ready.
1: Device configuration is locked.
The value after the USB device controller hardware reset is low; after USB
reset, it is unchanged (keep previous configuration).
USB Device Controller
Universal Serial Bus (USB) 79