Texas Instruments OMAP5912 Reference Manual page 1381

Table 43. DMA Interrupt Enable Register (DMA_IRQ_EN) (Continued)
Bit Name
6 TX1_DONE_IE
5 RX1_CNT_IE
4 RX1_EOT_IE
3 Reserved
2 TX0_DONE_IE
1 RX0_CNT_IE
0 RX0_EOT_IE
Table 44. Interrupt Source Register (IRQ_SRC)
Bit Name
15:11 Reserved
10 TXn_DONE
SPRU761A
Description
Transmit DMA channel 1 done interrupt enable
Receive DMA channel 1 transactions count interrupt enable
Receive DMA channel 1 end of transfer interrupt enable
Reserved
Transmit DMA channel 0 done interrupt enable
Receive DMA channel 0 transactions count interrupt enable
Receive DMA channel 0 end of transfer interrupt enable
This read/write register enables all DMA interrupts.
When the USB device controller sets a bit position to 1, an interrupt is signaled
to the USB device controller if the corresponding bit in the IRQ_SRC register
is asserted to 1 by the core. If reset to 0, the interrupt is masked and not
signaled to the USB device controller.
-
0: Interrupt is disabled.
-
1: Interrupt is enabled.
The value after MPU or USB reset is low for all bits.
Description
Reserved
The transmit DMA channel n done interrupt flag (non-ISO) bit is only for non-ISO
DMA transfer. This bit is never set for ISO DMA transfer.
The core automatically sets this bit when a transmit DMA channel has completed
the programmed transfer by servicing the last IN transaction from the USB host.
This is when TXDMAn.TXn_TSC (transfer size counter) equals 0, and the last IN
transaction completes with an ACK. When this bit is asserted, the USB device
controller must read the DMAN_STAT register to identify the endpoint number for
which the transfer completed.
The endpoint interrupt IRQ_SRC.EPn_TX is never set for the assigned endpoint
to TX DMA channel n.
0: No action
1: Non-ISO transmit DMA transfer for a channel has ended.
The value after MPU or USB reset is low.
USB Device Controller
Universal Serial Bus (USB) 89