Texas Instruments OMAP5912 Reference Manual page 1229

UARTs
Table 91. Mode Definition Register 1 (MDR1) (Continued)
Bit Name
5 SCT
4 SET_TXIR
3 IR_SLEEP
2:0 MODE_SELECT
164 Serial Interfaces
Function
Store and control the transmission
0: Starts the IrDA transmission as soon as a value is
written to THR.
1: Starts the IrDA transmission with the control of
ACREG[2].
Used to configure the IrDA transceiver
0: No action.
1: TXIR pin output is forced high.
0: IrDA sleep mode disabled.
1: IrDA sleep mode enabled.
000: UART 16x mode
001: SIR mode
010: UART 16x autobaud
011: UART 13x mode
100: MIR mode
101: FIR mode
110: Reserved
111: Disable (default state)
Offset Address (hex): 0x09 x S
IrDA modes only.
MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN
bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The
bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries)
and must be programmed before the mode is programmed in MDR1[2:0].
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 111
SPRU760B