Texas Instruments OMAP5912 Reference Manual page 1219

UARTs
Table 70. Line Status Register (LSR) (IR Mode) (Continued)
Bit Name
1 STS_FIFO_E
0 RX_FIFO_E
Table 71. Supplementary Status Register (SSR)
Bit Name
7:2 −
1 RX_CTS_DSR_WAKE
_UP_STS
0 TX_FIFO_FULL
Table 72. Modem Control Register (MCR)
Bit Name
7 −
6 TCR_TLR
5 XON_EN
154 Serial Interfaces
Function
0: Status FIFO not empty.
1: Status FIFO empty.
0: At least one data character in the RX_FIFO.
1: No data in the receive FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [FL, CRC, ABORT] of
the frame at the top of the STATUS FIFO (next frame status to be read). See
Table 110, IrDA Mode Interrupts.
Offset Address (hex): 0x11 x S and read
Function
Reserved
0: No falling edge event on RX, CTS and DSR.
1: A falling edge occurred on RX, CTS or DSR.
0: TX FIFO not full.
1: TX FIFO full.
Bit 1 is reset only when SCR[4] is reset to 0.
Offset Address (hex): 0x04 x S and LCR is not 0xBF (and EFR[4] = 1 for
MCR[7:5])
MCR[3:0] controls the interface with the modem, data set, or peripheral device
that is emulating the modem.
Function
Reserved.
0: No action.
1: Enables access to the TCR and TLR registers.
0: Disable the XON any function.
1: Enable the XON any function.
R/W Reset
R 1
R 1
R/W Reset
R 000000
R 0
R 0
R/W Reset
R 0
R/W 0
R/W 0
SPRU760B