Texas Instruments OMAP5912 Reference Manual page 1415

3.6.2 Isochronous IN Transaction Error Conditions
3.6.3 Isochronous IN Endpoint FIFO Error Conditions
3.7 Control Transfers on Endpoint 0
SPRU761A
isochronous endpoints always return 0. Because there is no handshake, there
is no endpoint-specific interrupt to the MPU to report handshake results for
isochronous endpoints.
If the USB host did not successfully complete an ISO IN transaction in the
previous frame, and if data were present in TX FIFO to be sent at the IN
transaction, the STAT_FLG.MISS_IN bit is asserted for the duration of the
following frame. If the ISO IN endpoint is cleared in the middle of a USB
transaction
to the background FIFO, the macro forces a bit stuffing error for the ISO
transaction.
If the MPU attempts to overfill the configured endpoint FIFO, data written to
DATA register after the TX FIFO is full is lost, but any data that was successfully
put into the FIFO is transmitted when that FIFO is the background FIFO and
an IN transaction for that endpoint occurs. Because an ISO TX FIFO is cleared
automatically on the toggle from background to foreground, there is no reason
to clear the FIFO. However, if the MPU does not wish to send the data it wrote,
clearing the endpoint is the only mechanism to do this.
Control transfers on endpoint 0 include control write and control read transfers.
Control write and control read transfers are each composed of two or more
transactions to endpoint 0. Additionally, the USB device controller module is
capable of autodecoding some control write and control read transfers. These
operations are summarized in Figure 8 and Figure 9. An IN or an OUT
transaction is received out of a control request. This transaction is
automatically stalled by the core.
USB Device Controller
Universal Serial Bus (USB) 123