Texas Instruments OMAP5912 Reference Manual page 1265

UARTs
6.6.14 Store and Controlled Transmission (SCT)
6.6.15 Underrun During Transmission
6.6.16 Overrun During Receive
6.6.17 Status FIFO
200 Serial Interfaces
In SCT the local host first starts writing data into the TX FIFO. Then, after it
writes a part of a frame for a bigger frame, or a whole frame (a small frame,
that is, a supervisory frame), it writes a 1 to ACREG[2] (deferred TX start) to
start transmission. SCT is enabled when MDR1[5] = 1. This method of
transmission differs from the normal mode, where transmission of data starts
immediately after data is written to the TX FIFO. SCT is useful for sending short
frames without TX underrun.
Underrun in transmission occurs when the TX FIFO becomes empty before
the end of the frame is transmitted. When underrun occurs, the device closes
the frame with end flags but attaches an incorrect CRC value. The receiving
device detects a CRC error and discards the frame; it can then ask for a
retransmission. Underrun also causes an internal flag to be set, which disables
further transmission. Before the next frame can be transmitted the system (LH)
must:
Reset the TX FIFO.
-
Read the RESUME register. This clears the internal flag.
-
This functionality is disabled with ACREG[4], compensated by the extension
of the stop bit in transmission in case the TX FIFO is empty.
Overrun occurs during receive if the RX state machine tries to write data into
the RX FIFO when it is already full. When overrun occurs, the device interrupts
the local host with IIR[3] and discards the remaining portion of the frame.
Overrun also causes an internal flag to be set, which disables further
reception. Before the next frame can be received the system (LH) must:
Reset the RX FIFO.
-
Read the RESUME register. This clears the internal flag.
-
In IrDA modes, a status FIFO is used to record the received frame status.
When a complete frame is received, the length of the frame and the error bits
associated with it are written into the status FIFO.
The frame length and error status can be determined by reading SFREGL/H
and SFLSR. Reading the SFLSR causes the read pointer to be incremented.
The status FIFO is eight entries deep and therefore can hold the status of eight
frames.
SPRU760B