Texas Instruments OMAP5912 Reference Manual page 1370

USB Device Controller
Table 36. Status Register (STAT_FLG) (Continued)
Bit Name
2 FIFO_EN
1 NON_ISO_FIFO_EMPTY
0 NON_ISO_FIFO_FULL
78 Universal Serial Bus (USB)
Description
The FIFO enable status (non-ISO) bit only concerns non-ISO
endpoints.This bit is asserted when CTRL.SET_FIFO_EN is set to 1
and is cleared automatically after a transaction completes with an
ACK, STALL.
0: The non-ISO endpoint FIFO is disabled.
1: The non-ISO endpoint FIFO is enabled.
Value after MPU or USB reset is low.
The non-ISO FIFO empty bit only concerns non-ISO endpoints.This
bit is set when the FIFO for the selected non-ISO endpoint is empty,
either via an appropriate CTRL.CLR_EP bit or CTRL.RESET_EP bit
or after successful reads from the selected FIFO.
0: Non-ISO FIFO is not empty.
1: Non-ISO FIFO isempty.
Value after MPU or USB reset is high (FIFO empty).
The non-ISO FIFO full bit only concerns non-ISO endpoints.This bit is
set when the FIFO for the selected non-ISO endpoint is full. This
condition is cleared by setting the CTRL.CLR_EP bit or
CTRL.RESET_EP bit, or after one successful read (by the USB
device controller or the USB host).
0: Non-ISO FIFO is not full.
1: Non-ISO FIFO is full.
Value after MPU or USB reset is low (FIFO empty).
This read-only register provides a status of the FIFO and the results of the
transactions handshakes for the selected endpoint. The 8 MSB are reserved
for ISO endpoints, whereas the 8 LSB are reserved for non-ISO endpoints.
This register cannot be read if EP_NUM.EP_SEL bit is not asserted for the
endpoint. No status flag exists for the read-only set-up FIFO, which is always
enabled.
SPRU761A