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2.6
USB Host Controller Registers, USB Reset, and USB Clocking
Table 30. USB Host Controller Clock Control
OTG_SYS-
MOD_CONF_CTRL_0.
CON_
CONF_MOD_USB_HOST_
2 OTG_
HHC_UHOST_EN_R
PADEN
0
0
1
1
2.7
OHCI Interrupts
SPRU761A
When the USB host controller clock is disabled, or when the ULPD does not
provide 48 MHz to the USB host controller, reads from and writes to the USB
host controller registers do not occur correctly. To properly access the USB
host controller registers, the USB host controller must be clocked and must be
out of reset.
USB host controller clock enable is controlled as described in Table 30.
Don't care
Don't care
0
1
The
USB
host
controller
ARM_RSTCT2.PER_EN bit and the OTG_SYSCON_1.SOFT_RESET bit.
The USB host controller is held in reset whenever ARM_RSTCT2.PER_EN is
0 or OTG_SYSCON_1.SOFT_RESET is 1. The USB host controller can
transition
out
of
ARM_RSTCT2.PER_EN is 1 and OTG_SYSCON_1.SOFT_RESET is 0.
The USB host controller completes its reset within about 72 cycles of the
48-MHz clock after the host controller clock is transitioned from disabled to
enabled using the mechanisms shown in Table 30 and the host controller reset
is removed. After system software turns on the clock to the USB host controller
and removes it from reset, it is necessary to wait until the USB host controller
internal reset completes. To ensure that the USB host controller has
completely reset, system software must wait until reads of both the
HCREVISION register and the HCHCCA register return their correct reset
default values.
The OMAP5912 USB host controller provides an interrupt output to the MPU
level 2 interrupt handler on its IRQ_06 interrupt input. This is a level-sensitive
interrupt signal, and the MPU level 2 interrupt handler IRQ_06 must be
programmed as a level-sensitive input.
OTG_
USB Host Clock
SYSCON2
Enabled?
UHOST_EN
0
No
1
Yes
Dont care
No
Dont care
Yes
hardware
reset
reset
whenever
the
Universal Serial Bus (USB)
USB Host Controller
USB Host in Reset?
Yes
No
Yes
No
is
controlled
by
clock
is
enabled
the
and
61
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