Texas Instruments OMAP5912 Reference Manual page 1423

Multimedia processor device overview and architecture
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Non-Autodecoded Control Write Transfer Error Conditions
3.7.4
Non-Autodecoded Control Read Transfers
SPRU761A
Status
stage
handshaking
STAT_FLG.FIFO_EN
completion of a non-autodecoded control write transfer is indicated by the USB
device controller module returning a zero length data payload for the data
phase of the status stage and an ACK handshake from the host for the
handshake phase of the status stage. Although NAK handshaking can be
used to indicate delays in completion of the requested control write, the USB
host can choose to abort the control write after some number of NAKs.
If an error occurs while dealing with the control write, which the MPU cannot
deal with itself, it must signal STALL to the USB host for all subsequent
transactions until a new setup token to endpoint 0 occurs. This is true for both
data stage and status stage transactions. This is most conveniently done by
setting endpoint 0 SYSCON2.STALL_CMD bit, which causes stalling of all the
remaining transactions of all remaining stages of a non-autodecoded control
transfer, up to the reception of the next valid SETUP command.
Error conditions are handled as for BULK/INTERRUPT transactions. If a
packet is received corrupted, the core ignores the transaction and no interrupt
is asserted.
Non-autodecoded
GET_INTERFACE_STATUS, GET_CONFIGURATION, GET_INTERFACE,
GET_DESCRIPTOR, SYNCH_FRAME and class- or vendor-specific control
read transfers. Non-autodecoded control read transfers consist of three
stages (setup, data, and status).
The setup stage of a valid non-autodecoded control read transfer consists of
one SETUP transaction from USB host to USB device. At the end of the setup
stage handshake, the USB module generates a MPU general USB interrupt
with the IRQ_SRC.SETUP flag set. The MPU must respond to this general
USB interrupt by setting the EP_NUM.SETUP_SEL bit, which clears the setup
interrupt flag. The MPU must then read 8 bytes from the setup FIFO via the
DATA
register,
clear
IRQ_SRC.SETUP flag. If the IRQ_SRC.SETUP flag is set, the MPU must
discard the setup data it has just read and handle the new setup data packet
following the same scheme. If the IRQ_SRC.SETUP flag is cleared, the MPU
code interprets this request information and then prepares data for the IN
transaction that follow. This includes placing the data being requested (or the
first few bytes, if more than one FIFO worth of data is being returned) into the
endpoint 0 FIFO, and setting the CTRL.SET_FIFO_EN bit.
is
controlled
and
SYSCON2.STALL_CMD
control
read
the
EP_NUM.EP_SEL
Universal Serial Bus (USB)
USB Device Controller
by
the
endpoint
bits.
Successful
transfers
include
bit,
and
check
0
the
the
131

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