Texas Instruments OMAP5912 Reference Manual page 1383

Multimedia processor device overview and architecture
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Table 44. Interrupt Source Register (IRQ_SRC) (Continued)
Bit
Name
7
SOF
6
Reserved
5
EPn_RX
4
EPn_TX
3
DS_CHG
SPRU761A
Description
Start of frame interrupt flag bit: every millisecond, the USB host outputs a
start-of-frame packet to the functions. The SOF bit reflects when a new SOF is
received. Writing a 1 in the SOF bit location clears the flag. Writing a 0 has no
effect.
In accordance with the USB1.1 specification, if SOF is received corrupted or is
not received, the core still sets this flag at the same rate (if bit SOF.FT_LOCK = 1)
or after 12043 USB bit time (if bit SOF.FT_LOCK = 0).
0: No action
1: Start-of-frame packet received (or internal SOF)
The value after MPU or USB reset is low.
Reserved
The EPn OUT transactions interrupt flag bit only concerns non-ISO endpoints.
The core automatically sets the EPn_RX bit when a handshake sequence occurs
for an OUT transaction to an interrupt of the bulk endpoint (NAK with
SYSCON1.NAK_EN set, ACK or STALL). The USB device controller must read
the EPn_STAT register to identify the endpoint causing the interrupt.
0: No action
1: OUT transaction detected on an endpoint
The value after MPU or USB reset is low.
The EPn IN transactions interrupt flag bit only concerns non-ISO endpoints.
The core automatically sets this bit when a handshake sequence occurs for an IN
transaction to an interrupt of bulk endpoint (NAK with SYSCON1.NAK_EN set,
ACK or STALL). The USB device controller must read the EPn_STAT register to
identify the endpoint causing the interrupt.
0: No action
1: IN transaction detected on an endpoint value after
MPU or USB reset is low.
Device state changed interrupt flag bit: the core automatically resets the DS_CHG
bit when the state of the device changes. This is when the core modifies any of
the bits present in the DEVSTAT register. When this bit is cleared, the background
DEVSTAT register moves into foreground position.
0: No action
1: Device state change detected
Value after USB device controller hardware reset is low and after USB reset is
high.
USB Device Controller
Universal Serial Bus (USB)
91

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