Texas Instruments OMAP5912 Reference Manual page 1223

UARTs
Table 75. Interrupt Enable Register (IER) (IrDA Mode) (Continued)
Bit Name
1 THR_IT
0 RHR_IT
Table 76. Interrupt Identification Register (IIR) (UART Mode)
Bit Name
7:6 FCR_MIRROR
5:1 IT_TYPE
0 IT_PENDING
Table 77. IrDA Mode Register (IIR)
Bit Name
7 EOF_IT
6 LINE_STS_IT
5 TX_STATUS_IT
4 STS_FIFO_IT
158 Serial Interfaces
Function
0: Disables the THR interrupt.
1: Enables the THR interrupt.
0: Disables the RHR interrupt.
1: Enables the RHR interrupt.
The TX_STATUS_IT interrupt reflects two possible conditions. The MDR2[0]
must be read to determine the status in the event of this interrupt.
Offset Address (hex): 0x02 x S and LCR is not 0xBF and read.
The IIR is a read-only register that provides the source of the interrupt in a
prioritized manner.
Function
Mirror the contents of FCR[0] on both bits
0: An interrupt is pending (UART_nIRQ active).
1: No interrupt is pending (UART_nIRQ inactive).
The UART_nIRQ output is activated whenever one of the eight interrupts is
active.
Function
0: Received EOF interrupt inactive.
1: Received EOF interrupt active.
0: Receiver line status interrupt inactive.
1: Receiver line status interrupt active.
0: TX status interrupt inactive.
1: TX status interrupt active.
0: Status FIFO trigger level interrupt inactive.
1: Status FIFO trigger level interrupt active.
R/W Reset
R/W 0
R/W 0
R/W Reset
R 00
R 00000
R 1
R/W Reset
R 0
R 0
R 0
R 0
SPRU760B