Texas Instruments OMAP5912 Reference Manual page 1384

USB Device Controller
Table 44. Interrupt Source Register (IRQ_SRC) (Continued)
Bit Name
2 SETUP
1 EP0_RX
0 EP0_TX
92 Universal Serial Bus (USB)
Description
Setup transaction interrupt flag bit: the core automatically sets the SETUP bit
when a valid setup transaction completes on control endpoint for a
non-autodecoded control request and automatically clears it when the USB
device controller sets EP_NUM.SETUP_SEL bit when reading setup data. A write
1 to it has no effect.
0: No action
1: Valid setup transaction occurred on endpoint 0.
Value after MPU or USB reset is low.
EP0 OUT transactions interrupt flag bit: the core automatically sets the EP0_RX
bit when a handshake sequence occurs for a non-autodecoded OUT transaction
to control endpoint (NAK with SYSCON1.NAK_EN set, ACK or STALL).
0: No action
1: OUT transaction on EP0
Value after MPU or USB reset is low.
EP0 IN transactions interrupt flag bit: the core automatically sets this bit when a
handshake sequence occurs for a non-autodecoded IN transaction to control
endpoint (NAK with SYSCON1.NAK_EN set, ACK or STALL).
0: No action
1: IN transaction on EP0
Value after MPU or USB reset is low.
This read/clear only register identifies and clears the source of the interrupt
signaled by a set flag.
The value depends on whether the reset action comes from the USB device
controller (MPU) or the USB host.
The USB device controller can clear a set bit location only by writing a 1 into
the bit location (except for the setup bit, which is automatically cleared by the
core). A write 0 has no effect.
When the core sets a bit location to 1, an interrupt is signaled to the USB device
controller if the interrupt was enabled.
-
0: No interrupt
-
1: Interrupt signaled
The value after the MPU or USB reset is low except for the
IRQ_SRC.DS_CHG bit, which is high after a USB reset.
SPRU761A