Texas Instruments OMAP5912 Reference Manual page 1227

UARTs
Table 85. Divisor Latches LowRegister (DLL)
Bit Name
7:0 CLOCK_LSB
Table 86. Divisor Latches High Register (DLH)
Bit Name
7:6 −
5:0 CLOCK_MSB
Table 87. Transmission Control Register (TCR)
Bit Name
7:4 RX_FIFO_TRIG_START RCV FIFO trigger level to RESTORE transmission
3:0 RX_FIFO_TRIG_HALT
Notes: 1) Trigger levels from 0 − 60 bytes are available with a granularity of 4.
(Trigger level = 4 x [4-bit register value])
2) The programmer must ensure that TCR[3:0] > TCR[7:4] whenever auto-RTS or software flow control is enabled,
to prevent device malfunction.
3) In FIFO interrupt mode with flow control, the programmer also must ensure that the trigger level to HALT transmis-
sion is greater than or equal to the receive FIFO trigger level (either TLR[7:4] or FCR[7:6]). Otherwise, the FIFO
operation stalls. This problem does not exist in FIFO DMA mode with flow control because a DMA request is sent
each time a byte is received.
Table 88. Trigger Level Register (TLR)
Bit Name
7:4 RX_FIFO_TRIG_DMA
3:0 TX_FIFO_TRIG_DMA
162 Serial Interfaces
Function
Used to store the 8-bit LSB divisor value
Offset Address (hex): 0x01 x S and LCR[7] = 1
Function
Reserved
Used to store the 6-bit MSB divisor value
Offset Address (hex): 0x06 x S and EFR[4] = 1 and MCR[6] = 1
This register stores the receive FIFO threshold levels to start/stop
transmission during hardware/software flow control.
Function
(0 − 60)
RCV FIFO trigger level to HALT transmission
(0 − 60)
Offset Address (hex): 0x07 x S and EFR[4] = 1 and MCR[6] = 1
This register stores the programmable transmit and receive FIFO trigger levels
used for DMA and IRQ generation.
Function
RCV FIFO trigger level
Transmit FIFO trigger level
R/W Reset
R/W 0x00
R/W Reset
R 00
R/W 000000
R/W Reset
R/W 0x0
R/W 0xF
R/W Reset
R/W 0x0
R/W 0x0
SPRU760B