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3.10
USB Device Interrupt Service Routine (ISR) Flowcharts
3.11
Important Note on USB Device Interrupts
SPRU761A
The flowcharts in this section give general operational guidelines for USB
device ISR processing. System-architecture-specific details are left to the
engineers who write the MPU and USB host code. One USB-specific interrupt
register is provided (IRQ_SRC), including:
-
General USB interrupts (including endpoint 0, DMA and device states
interrupts) on MPU level 2 IRQ_20
-
Non-ISO endpoint-specific interrupt on MPU level 2 IRQ_30
-
Start of frame (SOF) interrupt for ISO transactions on MPU level 2 IRQ_29
The general USB interrupt ISR must handle non-autodecoded control
transfers on endpoint 0 and some specialty interrupts generated because of
USB device state modifications or DMA transfers. The ISR for the
endpoint-specific interrupt must handle interrupts from the USB module that
are generated because of USB activity for non-isochronous endpoints. The
SOF ISR is responsible for handling isochronous endpoints and, if needed by
the application, tracking the USB frame number. Many flowcharts are
presented in this chapter to provide guidelines for how to handle the interrupts
related to the USB device controller module. The flowcharts in this part
suppose that the SYSCON1.NAK_EN bit is cleared.
Note:
A key assumption behind the flowcharts presented here is that the applica-
tion provides separate buffers for each direction of endpoint, except for end-
point 0. The flowcharts read from these application buffers for IN transac-
tions on TX endpoints and write to these application buffers for OUT transac-
tions on RX endpoints.
The USB device controller does not support reentrant interrupts. Each USB
device controller must be handled completely before handling another USB
device controller interrupt. This restriction occurs because there is only one
EP_NUM register, so endpoint control operations must be completed before
working with another endpoint or endpoint direction.
When an endpoint interrupt is asserted, the MPU writes the EP_NUM register
with the EP_NUM.EP_SEL bit set to 1. The MPU must finish the interrupt
handling before clearing the EP_NUM.EP_SEL bit, because clearing this bit
clears the corresponding status bit in the STAT_FLG register (ACK, NAK,
STALL). When an interrupt is pending on an endpoint, the MPU must not select
and then unselect the endpoint without handling the interrupt, because this
USB Device Controller
Universal Serial Bus (USB)
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