Texas Instruments OMAP5912 Reference Manual page 1438

USB Device Controller
3.12 Parsing General USB Device Interrupt
146 Universal Serial Bus (USB)
clears the pending transaction status flags. The MPU does not need to set
EP_NUM.EP_SEL
CTRL.SET_HALT, and CTRL.CLR_HALT bits.
The endpoint status (STAT_FLG register) is updated at the end of each USB
transaction if the previous transaction has been handled. If a pending interrupt
has not been handled when a new non-transparent transaction occurs, status
flags are not updated (and NAK is returned, even if FIFO was enabled, or
STALLed if the EP halt feature was set), so that the MPU never misses an
ACKed transaction. If double-buffering is used for an endpoint, STAT_FLG is
updated if there is zero or one interrupt pending for the endpoint, and is not
updated if there are already two interrupts pending on the endpoint.
The MPU does not need to set the SYSCON1.NAK_EN bit during normal
operation. However, for debugging process, this bit can be set when the MPU
finishes handling an EP interrupt without having set the corresponding
CTRL.SET_FIFO_EN bit. During TX transaction, if the SYSCON1.NAK_EN
bit is set, the MPU must wait for a NAK interrupt to write the TX data, to avoid
a possible conflict caused by the NAK interrupt received while the MPU was
writing the TX data.
The general USB interrupt (MPU level 2 IRQ_20) ISR must parse the interrupt
identifier register IRQ_SRC to determine the types of general USB interrupts
that are active. These include interrupts relating to USB device state
modifications (USB reset, suspend/resume, during enumeration phase) and
control transfers on endpoint 0 or non-ISO DMA transfers in either receive or
transmit mode. Multiple interrupts can be active at any time, and all must be
dealt with by the ISR before returning from the ISR. Figure 15 shows an
appropriate flowchart for parsing the general USB interrupts.
to 1 when setting CTRL.SET_FIFO_EN,
SPRU761A